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mos integrated circuit the information in this document is subject to change without notice. ? 1996 m m m m pd431636l 1m-bit cmos synchronous fast sram 32k-word by 36-bit pipelined operation document no. m12179ej5v0ds00 (5th edition) date published july 1998 ns cp(k) printed in japan data sheet the mark ? ? ? ? shows major revised points. description the m pd431636l is a 32,768-word by 36-bit synchronous static ram fabricated with advanced cmos technology using n-channel four-transistor memory cell. the m pd431636l integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as sram core. all input registers are controlled by a positive edge of the single clock input (clk). the m pd431636l is suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. zz has to be set low at the normal operation. when zz is set high, the sram enters power down state (sleep). in the sleep state, the sram internal state is preserved. when zz is set low again, the sram resumes normal operation. the m pd431636lgf is packaged in 100-pin plastic lqfp with a 1.4 mm package thickness for high density and low capacitive loading. features 3.3 v (chip) / 3.3 v or 2.5 v (i/o) supply synchronous operation internally self-timed write control burst read / write: interleaved burst and linear burst sequence fully registered inputs and outputs for pipelined operation all registers triggered off positive clock edge 3.3 v or 2.5 v lvttl compatible : all inputs and outputs fast clock access time: 4.6 ns (150 mhz), 5 ns (133 mhz) asynchronous output enable: /g burst sequence selectable: mode sleep mode: zz (zz = open or low : normal operation ) separate byte write enable: /bw1 - /bw4, /bwe global write enable: /gw three chip enables for easy depth expansion common i/o using three state outputs ordering information part number access time clock frequency package m pd431636lgf-a6 4.6 ns 150 mhz 100-pin plastic lqfp (14x20 mm) m pd431636lgf-a7 5.0 ns 133 mhz 100-pin plastic lqfp (14x20 mm) ? ?
2 m m m m pd431636l pin configuration(marking side) /xxx indicates active low si gnal. 100-pin plastic lqfp (14 x 20 mm) [ m m m m pd431636lgf] i/op3 i/o17 i/o18 v dd q v ss q i/o19 i/o20 i/o21 i/o22 v ss q v dd q i/o23 i/o24 nc v dd nc v ss i/o25 i/o26 v dd q v ss q i/o27 i/o28 i/o29 i/o30 v ss q v dd q i/o31 i/o32 i/op4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/op2 i/o16 i/o15 v dd q v ss q i/o14 i/o13 i/o12 i/o11 v ss q v dd q i/o10 i/o9 v ss nc v dd zz i/o8 i/o7 v dd q v ss q i/o6 i/o5 i/o4 i/o3 v ss q v dd q i/o2 i/o1 i/op1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 /bw4 /bw3 /bw2 /bw1 /ce2 v dd v ss clk /gw /bwe /g /ac /ap /adv a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc nc a10 a11 a12 a13 a14 nc nc ?
3 m m m m pd431636l pin identification symbol pin no. description a0 - a14 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48 synchronous address input i/o1 - i/o32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 synchronous data in, synchronous / asynchronous data out /op1 - i/op4 1, 30, 51, 80 synchronous data in (parity), synchronous / asynchronous data out (parity) /adv 83 synchronous burst address advance input /ap 84 synchronous address status processor input /ac 85 synchronous address status controller input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /bw1 - /bw4, /bwe 93, 94, 95, 96, 87 synchronous byte write enable input /gw 88 synchronous global write input /g 86 asynchronous output enable input clk 89 clock input mode 31 asynchronous burst sequence select input have to be tied to v dd or v ss during normal operation zz 64 asynchronous power down state input v dd 15, 41, 65, 91 power supply v ss 17, 40, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 14, 16, 38, 39, 42, 43, 49, 50, 66 no connection
4 m m m m pd431636l block diagram address register binary counter and logic clr q0 q1 byte 1 write register byte 1 write driver 9 byte 2 write register byte 2 write driver 9 byte 3 write register byte 3 write driver 9 byte 4 write register byte 4 write driver 9 enable register row & column decoder memory matrix 512 rows 64 36 columns (1,179,648 bits) output register output buffer input register 36 15 15 13 15 a0, a1 a1 a0 36 4 36 a0 - a14 mode /adv clk /ac /ap /bw1 /bw2 /bw3 /bw4 /bwe /gw /ce ce2 /ce2 /g i/o1 - i/o32 i/op1 - i/op4 enable delay register zz power down control burst sequence interleaved burst sequence table (mode = open or v dd ) external address a14 - a2, a1, a0 1st burst address a14 - a2, a1, /a0 2nd burst address a14 - a2, /a1, a0 3rd burst address a14 - a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a14 - a2, 0, 0 a14 - a2, 0, 1 a14 - a2, 1, 0 a14 - a2, 1, 1 1st burst address a14 - a2, 0, 1 a14 - a2, 1, 0 a14 - a2, 1, 1 a14 - a2, 0, 0 2nd burst address a14 - a2, 1, 0 a14 - a2, 1, 1 a14 - a2, 0, 0 a14 - a2, 0, 1 3rd burst address a14 - a2, 1, 1 a14 - a2, 0, 0 a14 - a2, 0, 1 a14 - a2, 1, 0
5 m m m m pd431636l asynchronous truth table operation /g i/o read cycle l dout read cycle h hi-z write cycle x hi-z, din deselected x hi-z remark x means dont care. synchronous truth table operation /ce ce2 /ce2 /ap /ac /adv /write clk address deselected note hxxx l x x l ? h n/a deselected note ll x l x x x l ? h n/a deselected note lxh l x x x l ? h n/a deselected note ll xh l x x l ? h n/a deselected note lxhh l x x l ? h n/a read cycle / begin burst l h l l x x x l ? h external read cycle / begin burst l h l h l x h l ? h external read cycle / continue burst x x x h h l h l ? hnext read cycle / continue burst h x x x h l h l ? hnext read cycle / suspend burst x x x h h h h l ? h current read cycle / suspend burst h x x x h h h l ? h current write cycle / begin burst l h l h l x l l ? h external write cycle / continue burst x x x h h l l l ? hnext write cycle / continue burst h x x x h l l l ? hnext write cycle / suspend burst x x x h h h l l ? h current write cycle / suspend burst h x x x h h l l ? h current note deselect status is held until new begin burst entry. remarks 1. x means dont care. 2. /write=l means any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) and /bwe are low or /gw is low. /write=h means the following two cases. (1) /bwe and /gw are high. (2) /bw1, /bw2, /bw3, /bw4 and /gw are high, and /bwe is low.
6 m m m m pd431636l partial truth table for write enables operation /gw /bwe /bw1 /bw2 /bw3 /bw4 read cycle h h x x x x read cycle h l h h h h write cycle / byte 1 only h l l h h h write cycle / all bytes h l l l l l write cycle / all bytes l x x x x x remark x means dont care. pass-through truth table previous cycle present cycle next cycle operation add /write i/o operation add /ces /write /g i/o operation read cycle (begin burst) am l h l q1(ak) read q1(am) write cycle ak l dn(ak) deselected - h x x hi-z no carry over from previous cycle remarks 1. x means dont care. 2. /write=l means any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) and /bwe are low or /gw is low. /write=h means the following two cases. (1) /bwe and /gw are high. (2) /bw1, /bw2, /bw3, /bw4 and /gw are high, and /bwe is low. /ces=l means /ce is low, /ce2 is low and ce2 is high. /ces=h means /ce is high or /ce2 is high or ce2 is low. zz (sleep) truth table zz chip status 0.2 v active open active 3 v dd - 0.2 v sleep
7 m m m m pd431636l electrical specifications absolute maximum ratings parameter symbol conditions min. typ. max. unit note supply voltage v dd C0.5 +4.6 v output supply voltage v dd q C0.5 v dd v input voltage v in C0.5 v dd + 0.5 v 1, 2 input / output voltage v i/o C0.5 v dd q + 0.5 v 1, 2 power dissipation p d C1.6w operating ambient temperature t a 0+70c storage temperature t stg C55 +125 c notes 1. C2.0 v (min.)(pulse width : 2 ns) 2. v ddq + 2.3 v (max.)(pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t a = 0 to 70 c) for 2.5 v lvttl interface parameter symbol conditions min. typ. max. unit supply voltage v dd 3.135 3.3 3.465 v output supply voltage v dd q 2.375 2.5 2.9 v high level input voltage v ih 1.7 v dd q + 0.3 v low level input voltage v il C0.3 note +0.7 v note C0.8 v (min.)(pulse width : 2 ns) for 3.3 v lvttl interface parameter symbol conditions min. typ. max. unit supply voltage v dd 3.135 3.3 3.465 v output supply voltage v dd q 3.135 3.3 3.465 v high level input voltage v ih 2.0 v dd q + 0.3 v low level input voltage v il C0.3 note +0.8 v note C0.8 v (min.)(pulse width : 2 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 4 pf input / output capacitance c i/o v i/o = 0 v 7 pf clock input capacitance c clk v clk = 0 v 4 pf remark these parameters are periodically sampled and not 100 % tested.
8 m m m m pd431636l dc characteristics (t a = 0 to 70 c, v dd = 3.3 v 0.165 v) parameter symbol test condition min. typ. max. unit note input leakage current i li v in (except zz, mode) = 0 v to v dd C2 +2 m a zz, mode = 0 v or v dd C5 +5 i/o leakage current i lo v i/o = 0 v to v dd q, outputs are disabled. C2 +2 m a operating supply current i cc device selected, cycle = max. -a6 220 ma v in v il or v in 3 v ih , i i/o = 0 ma -a7 200 -a6 60 i cc1 suspend cycle, cycle = max. /ac, /ap, /adv, /gw, /bwes 3 v ih v in v il or v in 3 v ih , i i/o = 0 ma -a7 50 standby supply current i sb device deselected, cycle = 0 mhz v in v il or v in 3 v ih , all inputs are static. 35 ma i sb1 device deselected, cycle = 0 mhz v in 0.2 v or v in 3 v dd - 0.2 v v i/o 0.2 v, all inputs are static. 0.5 20 i sb2 device deselected, cycle = max. v in v il or v in 3 v ih 50 140 power down supply current i sbzz zz 3 v dd C 0.2 v, v i/o v dd q + 0.2 v 0.5 20 ma 2.5 v lvttl interface high level output voltage v oh i oh = C2.0 ma 2.1 v low level output voltage v ol i ol = +2.0 ma 0.3 v 3.3 v lvttl interface high level output voltage v oh i oh = C4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v
9 m m m m pd431636l ac characteristics (t a = 0 to 70 c, v dd = 3.3 v 0.165 v) ac test conditions 2.5 v lvttl interface input waveform (rise / fall time 2.4 ns) test points v ss 2.4 v 1.2 v 1.2 v output waveform test points 1.2 v 1.2 v 3.3 v lvttl interface input waveform (rise / fall time 3.0 ns) test points v ss 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load condition c l : 30 pf 5 pf (tdc1, tdc2, tolz, tohz, tcz) figure1 external load at test v t = +1.2 v/+1.5 v i/o (output) 50 w z o = 50 w c l remark c l includes capacitances of the probe and jig, and stray capacitances. ?
10 m m m m pd431636l read and write cycle (2.5 v lvttl interface) parameter symbol -a6 (150 mhz) -a7 (133 mhz) standard alias min. max. min. max. unit note cycle time tkhkh tcyc 6.6 C 7.5 C ns clock access time tkhqv tcd C 4.6 C 5 ns output enable access time tglqv toe C 4.8 C 4.8 ns clock high to output active tkhqx1 tdc1 0 C 0 C ns clock high to output change tkhqx2 tdc2 1.5 C 1.5 C ns output enable to output active tglqx tolz 0 C 0 C ns output disable to output high-z tghqz tohz 0 4.8 0 4.8 ns clock high to output high-z tkhqz tcz 1.5 5 1.5 5 ns clock high pulse width tkhkl tch 1.8 C 1.9 C ns clock low pulse width tklkh tcl 1.8 C 1.9 C ns setup times address tavkh tas 2 C 2 C ns address status tadsvkh tss data in tdvkh tds write enable twvkh tws address advance tadvvkh C chip enable tevkh C hold times address tkhax tah 0.5 C 0.5 C ns address status tkhadsx tsh data in tkhdx tdh write enable tkhwx twh address advance tkhadvx C chip enable tkhex C power down entry setup tzzes tzzes 5 C 5 C ns 1 power down entry hold tzzeh tzzeh 1 C 1 C ns 1 power down recovery setup tzzrs tzzrs 6 C 6 C ns 1 power down recovery hold tzzrh tzzrh 0 C 0 C ns 1 note 1. although zz signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized.
11 m m m m pd431636l read and write cycle (3.3 v lvttl interface) parameter symbol -a6 (150 mhz) -a7 (133 mhz) standard alias min. max. min. max. unit note cycle time tkhkh tcyc 6.6 C 7.5 C ns clock access time tkhqv tcd C 4.6 C 5 ns output enable access time tglqv toe C 4.8 C 4.8 ns clock high to output active tkhqx1 tdc1 0 C 0 C ns clock high to output change tkhqx2 tdc2 1.5 C 1.5 C ns output enable to output active tglqx tolz 0 C 0 C ns output disable to output high-z tghqz tohz 0 4.8 0 4.8 ns clock high to output high-z tkhqz tcz 1.5 5 1.5 5 ns clock high pulse width tkhkl tch 2.5 C 2.5 C ns clock low pulse width tklkh tcl 3 C 3 C ns setup times address tavkh tas 2.5 C 2.5 C ns address status tadsvkh tss data in tdvkh tds write enable twvkh tws address advance tadvvkh C chip enable tevkh C hold times address tkhax tah 1 C 1 C ns address status tkhadsx tsh data in tkhdx tdh write enable tkhwx twh address advance tkhadvx C chip enable tkhex C power down entry setup tzzes tzzes 5 C 5 C ns 1 power down entry hold tzzeh tzzeh 1 C 1 C ns 1 power down recovery setup tzzrs tzzrs 6 C 6 C ns 1 power down recovery hold tzzrh tzzrh 0 C 0 C ns 1 note 1. although zz signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized.
12 m m m m pd431636l tkhkh tklkh tkhax twvkh tkhwx tkhex tglqv tglqx tkhqx2 tkhqz q1(a1) q1(a2) q2(a2) q3(a2) q4(a2) q1(a2) hi-z a1 a2 a3 clk /ap /ac address /adv /ces note /g data in /bwe /bws tghqz tkhqv tkhkl tkhadsx tadsvkh tavkh tevkh tadsvkh tkhadsx tadvvkh tkhadvx twvkh tkhwx /gw data out read cycle remark qn(a2) refers to output from address a2. q1-q4 refer to outputs according to burst sequence. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. note
13 m m m m pd431636l tkhkh tavkh tkhax tevkh tkhex d1(a1) d1(a2) d2(a2) d2(a2) d3(a2) d4(a2) d1(a3) d2(a3) d3(a3) hi-z tkhkl tklkh a1 a2 a3 tdvkh tkhdx tkhadsx twvkh tkhwx clk /ap /ac address /adv /ces note2 /g data in /bwe note1 /bws /gw note1 data out tadvvkh twvkh tkhadvx tkhwx tadsvkh tkhadsx tadsvkh write cycle notes 2. all bytes write can be initiated by /gw low or /gw high and /bwe, /bw1-/bw4 low. 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. tghqz
14 m m m m pd431636l tkhkh tklkh tkhkl tavkh tevkh tkhex tkhqv tglqx q1(a1) q1(a2) q1(a3) q2(a3) q3(a3) a3 a2 a1 tghqz tkhqx1 tdvkh tkhdx hi-z d1(a2) tadsvkh tkhadsx tkhax tadsvkh tkhadsx clk /ap /ac address /adv /ces note2 /g data in /bwe note1 /bws /gw note1 data out twvkh tkhwx twvkh tkhwx q4(a3) tadvvkh tkhadvx notes 2. all bytes write can be initiated by /gw low or /gw high and /bwe, /bw1-/bw4 low. 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. read / write cycle
15 m m m m pd431636l tkhkh zz tklkh a1 a2 tzzeh tzzes tzzrh tzzrs power down (i sbzz ) state q1(a2) q1(a1) tkhkl clk /ap /ac address /adv /ces /g /bwe /bws /gw data out power down (zz) cycle hi-z
16 m m m m pd431636l tkhkh data out tkhkl tklkh a1 a2 power down state (i sb1 ) note q1(a1) q1(a2) data in clk /ap /ac address /adv /ces /g /bwe /bws /gw stop clock cycle hi-z note v in 0.2 v or v in 3 v dd - 0.2 v, v i/o 0.2 v
17 m m m m pd431636l package drawing 100 pin plastic lqfp (14 20) item millimeters inches a i j 22.00.2 0.13 0.65 (t.p.) 0.8660.008 0.005 0.026 (t.p.) note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. f n p 1.4 0.10 0.004 0.055 q s detail of lead end b 20.00.2 0.787 c 14.00.2 0.551 d f g 16.00.2 0.575 0.825 0.6300.008 0.032 0.023 h 0.32 0.0130.003 k 1.00.2 0.039 l 0.50.2 0.020 m 0.17 0.0070.002 +0.06 C0.05 s100gf-65-8et q 0.1250.075 0.0050.003 r3 +7 3 +7 s 1.7 max. 0.067 max. +0.08 C0.07 +0.008 C0.009 +0.009 C0.008 +0.009 C0.008 +0.009 C0.008 m a r gh i j c d k m l n p 80 81 51 50 30 31 100 1 b C3 C3
18 m m m m pd431636l recommended soldering condition please consult with our sales offices for soldering conditions of the m pd431636l. type of surface mount devices m pd431636lgf : 100-pin plastic lqfp (14 x 20 mm) ?
19 m m m m pd431636l notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m pd431636l [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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